1. Field of the Invention
The present invention relates to a digital data driver, and more particularly, to a digital data driver using a less number of output buffers, and a display device using the digital data driver.
2. Description of the Related Art
In the Liquid Crystal Display (LCD) device, the data driver (or referred as a source driver) controls and drives the LCD panel according to a digital input signal from the timing controller. FIG. 1A shows a block diagram of a conventional N-channel M-bit digital data driver, and FIG. 1B shows a timing diagram of the clock signal and the control signals of the conventional data driver. Referring to FIG. 1A, the data driver 100 comprises an input unit 110, a digital-to-analog (D/A) converting unit 120, and an output buffer 130. Wherein, the input unit 110 comprises a shift register 111, a first line latch 112, a second line latch 113, and a level shifter 114.
Referring to FIGS. 1A and 1B, the shift register 111 is triggered by the clock signal CLK and the first control signal CT1, and the second line latch 113 is controlled by the second control signal CT2. When the first control signal is transited to the high level, the shift register 111 sequentially shifts the received first control signal CT1 according to the clock signal CLK, and provides (N/3) latch signals of different phases to the first line latch 112. The first line latch 112 sequentially receives and latches the input digital data stream IN1, IN2, and IN3 according to a latch signal provided by the shift register 111, wherein the digital data stream IN1, IN2, and IN3 respectively represents the red (R), green (G), and blue (B) pixel data, and each pixel data is represented by M bits.
When the entire line latch is filled with the digital data stream that is sequentially latched in the first line latch 112, the second control signal CT2 transits to the high level, thus the digital data latched in the first line latch 112 is transmitted and latched in the second line latch 113 simultaneously. Then, the level shifter 114 converts the digital data latched in the second line latch 113 into the data with a higher voltage level so as to accurately drive the D/A converting unit 120. The D/A converting unit 120 receives the M-bits digital data D1˜D(N) that is provided by the level shifter 114 and converts the received digital data D1˜D(N) into the corresponding analog data A1˜A(N) such as the analog voltages. The output buffer 130 is configured to improve the driving capability of the analog data A1˜A(N), such that the digital data driver can drive the LCD panel accurately. Then, the clock signal CLK and the first control signal CT1 transit to the high level again, thus the data in the first line latch 112 is refreshed and latched, and the processes mentioned above are repeated.
FIG. 2 shows a detailed block diagram of the D/A converting unit 120 and the output buffer 130 of FIG. 1A. Referring to FIG. 2, the D/A converting unit 120 comprises N D/A converters 121˜12(N), and each D/A converter may comprise a decoder and a switch set. For example, the D/A converter 121 comprises a decoder DEC1 and a switch set SW1. In addition, the D/A converting unit 120 further comprises a grey-level voltage generator 140. The grey-level voltage generator 140 generates the grey-level voltages V1˜V(2M) of different levels by using the serially-connected resistors to divide the supply voltage difference (VDD−VSS). The output buffer 130 comprises N buffers BUF1˜BUF(N).
Using the D/A converter 121 as an example, first the decoder DEC1 receives the M-bit digital data D1 and decodes it to the digital data E1. Then, the switch set SW1 selects and outputs the analog data A1 corresponding to the decoded digital data E1 (or the digital data D1) among the grey-level voltages V1˜V(2M) according to the decoded digital data E1. Finally, the buffer BUF1 receives the analog data A1, such that the analog data OUT1 provided by the buffer BUF1 has enough driving ability to drive the LCD panel.
One embodiment of the D/A converter 121 is as shown in FIG. 3A, and the corresponding relationship between the decoded digital data E1 and the analog data A1 is as shown in FIG. 3B. In the present embodiment, the digital data D1 is, for example, represented by 2 bits, thus 22 grey-level voltages V1˜V4 are required. Accordingly, the purpose of the decoder DEC1 is to be adapted to the design of the switch set SW1, such that the received digital data D1 is decoded to the digital data E1 that is suitable for controlling the switch set SW1. Here, FIGS. 3A and 3B are only one of the designs. Another embodiment of the D/A converter 121 is as shown in FIG. 3C. In such case, the decoder is not required, and the corresponding relationship between the digital data D1 and the analog data A1 is as shown in FIG. 3D. In the present embodiment, the digital data D1 is, for example, represented by 2 bits, thus 22 grey-level voltages V1˜V4 are required. The digital data D1 can be directly applied to control the switch set SW1, and FIGS. 3C and 3D are only one of the designs.